RF switches are component devices commonly utilized in wireless communication devices (e.g., cellular or smart phones) to route high-voltage, low- and high-frequency signals through transmission paths between the device's processing circuitry and the device's antenna. State-of-the-art attenuation and antenna tuning applications in such wireless communication devices require RF switches capable of transmitting RF signals up to 70V and in the range of 0.5 GHz to 6 GHz with a high degree of linearity. To accommodate the high-power RF signals, current state-of-the-art RF switches typically utilize several low voltage (e.g., 2-5V) NMOS transistors connected in a stacked (drain-to-source) arrangement such that the high RF signal voltage is distributed evenly across the low voltage transistors. With this arrangement, a first RF switch can be turned on to route high frequency signals from a device's processing circuitry to the device's antenna during transmission-mode operations, and a second RF switch can be turned on to signals from the device's antenna to the device's processor during receiving-mode operations.
RF switches that are produced using silicon-on-insulator (SOI) technology (referred to herein as RF SOI switches) were developed in response to a demand for low-cost solid state RF switches utilized in cellular phones and other low-cost wireless communication devices. Silicon on insulator (SOI) technology refers to the use of a layered silicon-insulator-silicon substrate in place of conventional monocrystalline silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance, thereby improving performance. Early SOI technology was considered impractical for RF switch applications due to cutoff frequency and breakdown voltage problems, so early solid-state RF switches were typically generated using silicon-on-sapphire (SOS) and gallium-arsenide monolithic microwave integrated circuit (GaAs MMIC) technologies. However, due to recent advances in CMOS SOI technology that addressed the early problems, RF SOI switches produced using CMOS and SiGe BiCMOS flows (and in some instances using RF MEMS fabrication flows) are now recognized as achieving comparable operating characteristics to SOS and GaAs Monolithic microwave integrated circuit (MMIC) switches at a substantially lower cost. Moreover, because SOI technology uses standard technologies and standard cell libraries developed for CMOS, BiCMOS and RF MEMS fabrication flows, RF SOI switches can be integrated into larger system-on-chip (SOC) devices that further minimize fabrication costs.
RF SOI switches are field-effect transistor-type (FET-type) structures that are mainly distinguished from other FET-type transistors in that they are formed on/over isolated silicon pads (islands) of an SOI base substrate, but are otherwise produced using the same standard processes of the core (i.e., CMOS, BiCMOS or RF MEMS) fabrication flow that are utilized to simultaneously fabricate other circuit structures of a SOC device on the SOI base substrate. That is, the SOI substrate is processed using known techniques to generate spaced-apart silicon islands (i.e., portions of the topmost silicon layer that rests on and are entirely surrounded by insulating material, typically silicon dioxide). The structural elements of the RF SOI switch are then fabricated onto an associated silicon island using the same standard fabrication flow processes that are utilized to simultaneously generate other circuit structures of the SOC device. For example, the same standardized n-type or p-type dopant diffusion processes are utilized to form source/drain regions in both the silicon island (i.e., for the RF SOI switch) and in other portions of the topmost silicon (e.g., to produce transistors forming a processor circuit or other functional circuitry of the SOC device). Similarly, the same polycrystalline silicon (polysilicon) gate structure formation processes (e.g., poly deposition, mask and etch) are utilized to form the gate structures of the RF SOI switch, and to simultaneously form gate structures of the SOC device's functional circuitry. Next, the same pre-metal dielectric (PMD) layer formation process is utilized to form a PMD layer over the polysilicon gate structures of both the RF SOI switch and the other functional circuitry, and the same contact structure formation processes (e.g., mask, etch, metal deposition, and chemical mechanical polishing or other planarizing process) is used to form contacts to the source/drain regions in both the RF SOI switch and the functional circuitry. Subsequent backend processing (e.g., metallization and contact pad formation) are similarly simultaneously performed over both the RF SOI switch and the other functional circuitry of the SOC device.
As the demand for wireless communication devices capable of higher data-rate transmissions continues to grow, there is a concomitant demand for RF SOI switches that exhibit ever-improving operating characteristics. A conventional approach for improving the operating characteristics of an RF SOI switch is to minimize the switch's Ron·Coff, which is a common figure of merit used to rate the performance of RF switches. An RF SOI switch's Ron value is determined by measuring the resistance across the switch when turned on (e.g., in the NMOS case, when a high gate voltage is applied), and the RF SOI switch's Coff value is determined by measuring the capacitance across the switch when turned off. The Ron·Coff value is determined by multiplying a switch's measured Ron and Coff values, and therefore the operating characteristics of the RF switch can, in theory, be improved by way of reducing one or both of the Ron and Coff values. That is, reducing the Ron value would allow more of the RF signal to travel through the RF switch when turned on, and reducing the Coff value would prevent more of the RF signal from traveling through the switch when turned off. It is important to note that the figure of merit—Ron×Coff—is determined from not just one switch but the switch(s) environment(s). The environment of the device, includes the switch but can also include the wiring and interconnect, the substrate, packaging, and all the parasitics (R, L, C's) associated with the surrounding device or device arrays.
One challenge associated with improving the operating performance of RF SOI switches is additional cost associated with changes to an existing RF SOI switch design. That is, once a fabrication (e.g., CMOS) flow is established that facilitates formation of RF SOI switches of a particular type, the introduction of new structural features or materials or other design changes require either changes to the established fabrication flow to accommodate the design changes.
What are needed are structural features and methods that improve the operating characteristics (e.g., Coff and Ron) of RF SOI switches that address the problems presented above. What is particularly needed are structural features that can be used to improve the operating characteristics of existing RF SOI switches, and that are easily incorporated into established fabrication flows (e.g., CMOS, BiCMOS or RF MEMS) using minimal addition processing and without requiring modifications to the established flow's processes.